1. Field of the Invention
The present invention generally relates to dynamic random access memory devices and, more specifically, to a dynamic random access memory device (hereinafter simply referred to as DRAM) in which a peak value of current consumed in refresh operation is reduces.
2. Description of the Prior Art
FIG. 1 is a block diagram showing one example of a conventional DRAM. The DRAM shown in this figure is disclosed in, for example, Japanese Patent Publication Gazette No. 23397/1987. Referring to FIG. 1, the DRAM comprises divided two memory array blocks 100a and 100b. The memory array block 100a comprises memory cell arrays (MCA) 31a and 32a connected to a sense amplifer (SA) 41a, Y decoders (YD) 21a and 22a, and dummy cell columns (DCC) 51a and 52a. Similarly, the memory array block 100b comprises memory cell arrays 31b and 32b connected to a sense amplifier 41b, Y decoders 21b and 22b, and dummy cell columns 51b and 52b. An address buffer (AB) 80 for receiving external address signals Ao to An, from which X address signals Xo to Xn and Y address signals Yo to Yn are outputted. Four X decoders (XD) 11a, 12a, 11b and 12b, each connected to receive signals Xo to Xn, are connected to memory cell arrays 31a, 32a, 31b and 32b through word lines WL1a to WL2ma and WL1b to WL2mb, respectively. An input/output control circuit (IOC) 90 is connected to four memory cell arrays 31a to 32b through four I/O lines 93 to 96 so as to control input/output of data signals through a data input buffer (DIB) 91 and a data output buffer (DOB) 92 connected thereto.
There is a sense amplifier activating signal generating circuit (SAG) 70 generating an activating signal .phi.3 for activating two sense amplifiers with a sense amplifier decoder (SAD) 61 connected to the output thereof. The signal .phi.3 is outputted in response to an external RAS signal. The sense amplifier decoder 61 receives the signal .phi.3 and outputs signals .phi.3a and .phi.3b for selectively activating either one or both of the two sense amplifiers 41a and 41b in response to the X address signal Xn. The sense amplifiers 41a and 41b are activated in response to the signals .phi.3a and .phi.3b, respectively. The signal Xn is a signal of the most significant bit and generally used for a largest division of the memory cell array.
A refresh control circuit 71 is connected to receive an external RAS signal and an external CAS signal. It detects the fall of the CAS signal before the fall of the RAS signal so as to determine that the refresh mode is externally designated. In a DRAM having self refresh mode, the circuit 71 detects a REF signal for designating the self refresh mode. In either case, when the refresh operation is requested, a delayed signal .phi.4 is outputted to the sense amplifier decoder 61 in response to the detection.
In reading operation, the sense amplifier decoder 61 outputs either the signal .phi.3a or .phi.3b for activating one of the two sense amplifiers 41a and 41b in response to the X address signal Xn. A data signal stored in the memory cell is amplified by the activated sense amplifier 41a or 41b to be outputted through one of the I/O lines 93 to 96 and through the data output buffer 92.
In refresh operation, the sense amplifier decoder 61 outputs the signals .phi.3a and .phi.3b simultaneously for activating both sense amplifiers 41a and 41b. The data signals stored in the memory cells are amplified by the activated sense amplifiers 41a and 41b to be stored again in the memory cells. Such refresh operation is effected on the memory cells respectively connected to the word lines WL1a to WL2mb. More specifically, m word lines are successively selected by the X decoders 11a to 12b and the sense amplifiers 41a and 41b are activated every time to refresh the data signals in the memory cells connected to the word line.
FIG. 2 is a schematic diagram showing a part of the memory cell array 31a and the sense amplifier 41a connected through a bit line pair BLj and BLj. FIG. 3 is a timing chart illustrating the operation thereof. These are shown in, for example, Digest of Technical Papers pp. 252 and 253 of International Solid-State Circuits Conference 85 held in 1985.
Referring to FIG. 2, a memory cell M is connected between a bit line BLj and a word line WLi. The memory cell M comprises a capacitor Cs for storing a data signal and an NMOS transistor Qs for switching. The sense amplifier 31a comprises a CMOS flip flop connected between the bit lines BLj and BLj. The CMOS flip flop is constituted by PMOS transistors Q3 and Q4 and NMOS transistors Q1 and Q2. The flip flop is connected to a power supply Vcc and to the ground Vss through a PMOS transistor Q.sub.SP and through an NMOS transistor Q.sub.SN, respectively. The transistors Q.sub.SP and Q.sub.SN have their gates connected to receive activating signals .phi.3a and .phi.3a, respectively. An equalizing circuit comprises an NMOS transistor Q5 and a series connection of NMOS transistors Q6 and Q7 connected between the bit lines BLj and BLj. The gates of these transistors are connected to receive an equalizing signal EQ. An I/O gate comprises an NMOS transistor Q8 connected between the bit line BLj and an I/O line and an NMOS transistor Q9 connected between the bit line BLj and an I/O line. The transistors Q8 and Q9 have their gates connected to receive a signal Yj from a column decoder 21a.
In reading operation, first, the transistors Q5, Q6 and Q7 are turned on in response to a high level equalizing signal EQ and the bit line pair BLj and BLj are brought to a precharge voltage V.sub.BL (1/2 Vcc). Meanwhile, the sense amplifier power supply line L.sub.P and a sense amplifier ground line L.sub.N are also brought to V.sub.BL. After the fall of the external RAS signal, the signal EQ changes to low level. Thereafter, the word line signal WLi becomes high level and the switching transistor Qs of the memory cell M turns on. The voltage of the bit line BLj slightly changes upon reception of a signal from the memory cell M. Consequently, a slight voltage difference is generated between the bit line BLj having the voltage of V.sub.BL and the bit line BLj.
On this occasion, the signals .phi.3a and .phi.3a are changed to activate the sense amplifier 41a. The change of the signal .phi.3a is a little delayed from the change of the signal .phi.3a. As a result, the slight voltage difference generated between the bit lines is amplified by the sense amplifier 41a. Thereafter, a high level signal Yj is applied to the gates of the transistors Q8 and Q9 from the Y decoder 21a and the amplified data signal is applied to the I/O line pair through the transistors Q8 and Q9.
In the refresh operation, different from the above operation, the amplified data signal is not applied to the I/O line pair but only to the capacitor Cs of the memory cell.
FIGS. 4 and 5 are schematic diagrams showing conventional sense amplifier decoders 61 and 62, respectively. These figures are also shown in the above mentioned Japanese Patent Publication Gazette No. 23397/1987. Referring to FIG. 4, the sense amplifier 61 comprises a first parallel connection of NMOS transistors T9 and T10 and a second parallel connection of NMOS transistors T11 and T12 connected to receive an activating signal .phi.3 outputted from a sense amplifier activating signal generating circuit (SAG) 70 and an NMOS transistor T13 connected between output lines 3a and 3b. The transistor T9 has its gate connected to receive the above described X address signal Xn and the transistor T12 has its gate connected to receive the inverted signal Xn. The transistors T10, T11 and T13 have their gates connected together to receive a refresh control signal .phi.4. The signal .phi.4 is outputted from the refresh control circuit in the DRAM in response to an externally applied signal instructing the refresh operation. The decoded activating signals .phi.3a and .phi.3b are outputted from the sense amplifier decoder 61.
In the normal reading operation except the refresh operation, a low level refresh control signal .phi.4 is applied to turn off the transistors T10, T11 and T13. Meanwhile, either the transistor T9 or T10 is turned on in response to the X address signal Xn or Xn. Consequently, the sense amplifier decoder 61 passes the activating signal .phi.3 in response to the signal Xn and outputs either the decoded activating signal .phi.3a or .phi.3b.
In the refresh operation, a high level refresh control signal .phi.4 is applied to turn on the transistors T10, T11 and T13. Two output lines 3a and 3b are equalized by the transistor 13 whereby the offset of the timing for activating the sense amplifiers 41a and 41b can be prevented. Therefore, the sense amplifier decoder 61 passes the activating signal .phi.3 irrespective of the value of the signal Xn, and the signals .phi.3a and .phi.3b having the same value are simultaneously outputted.
Referring to FIG. 5, in the sense amplifier decoder 62 the transistors T10 and T11, which were shown in FIG. 4, are removed. The transistor T9 has the gate connected to receive the X address signal Xn and the refresh control signal .phi.4, and the transistor T12 has the gate connected to receive the signal Xn and the signal .phi.4. The operation is carried out in the similar manner as the sense amplifier decoder 61 shown in FIG. 4.
As described above, in the reading operation, the sense amplifiers 41a and 41b are activated for each of the divided memory array blocks, so that even if the storage capacitance of the DRAM is increased, the sensitivity is superior. Therefore, correct reading operation can be carried out with small power consumption.
FIGS. 6(a) and (b) are schematic diagrams showing the conventional sense amplifiers 41a and 41b. Referring to FIG. 6(a), the sense amplifier 41a comprises a number of CMOS flip flops connected between corresponding bit lines BL.sub.1 to BL.sub.K and BL.sub.1 to BL.sub.K. For example, the CMOS flip flop connected between the bit lines BL.sub.1 and BL.sub.1 comprises PMOS transistors Q3 and Q4 and NMOS transistors Q1 and Q2. As is apparent from the figure, the sense amplifier 41a comprises a number of CMOS flip flops which are activated by the activating signals .phi.3a and .phi.3a. Meanwhile, the sense amplifier 41b of FIG. 6(b) also comprises a number of CMOS flip flops which are activated by the signals .phi.3b and .phi.3b.
FIG. 7 is a timing chart showing the relation between the change of the current ISa consumed by the activation of two sense amplifiers 41a and 41b in the refresh operation and the activating signals .phi.3a, .phi.3a, .phi.3b and .phi.3b. As described above, in the refresh operation, two sense amplifiers 41a and 41b are simultaneously activated and the data signals stored in the memory cells are amplified. Consequently, a sense amplifier consumption current Isa with a large peak value I.sub.1 is consumed, causing the following problems. Namely, since a large current Isa is consumed in a short period of time in the DRAM, the voltage of the power supply Vcc drops. By the decrease of the power supply voltage, the sensitivity of the sense amplifiers 41a and 41b is degraded and malfunctions of other circuits in the DRAM are caused. In addition, it becomes difficult to design the memory board, on which the DRAM is applied, to avoid these problems.
An example of the prior art of particular interest to the present invention is disclosed in Digest of Technical Papers pp. 232-233 of the International Solid-State circuits Conference (ISSCC 83). In this example, a memory cell array in a DRAM is divided into 8 blocks and 4 blocks thereof are selectively activated.
Another example of the prior art of interest to the present invention is disclosed in Digest of Technical Papers pp. 96-97 of International Solid-State Circuits Conference (ISSCC 84). This article shows a circuit for shifting precharge timing of every matrix in the DRAM.